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E85 Digital Design

Chapter 1b: logic gates, noise margins, transistors, power usage

Profile picture of Samson ZhangSamson Zhang
Jan 17, 20243 min read

Logic gates

Here's the notation and naming for some logic gates. Not going into detail with truth tables and such because I think they're pretty intuitive.



Note that multi-input XOR gates don't output true if only one input is true. Instead, they output true if an odd number of inputs (1, 3, 5...) are true.

Noise margins

Noise margins arise from choosing the values at which a voltage is treated as a logic 1 or 0. An output stage puts out

V_{OL} VOL V_{OL}
below which is 0 and
V_{OH} VOH V_{OH}
is 1. An input stage sees below
V_{IL} VIL V_{IL}
as 0 and above
V_{IH} VIH V_{IH}
as 1. Noise margins thus arise
NM_H = V_{OH} - V_{IH}, NM_L = V_{IL} - V_{OL} NMH=VOH−VIH,NML=VIL−VOL NM_H = V_{OH} - V_{IH}, NM_L = V_{IL} - V_{OL}
.

To maximize noise margins, choose

V_{IH}, V_{IL} VIH,VIL V_{IH}, V_{IL}
at "unity gain points" in the component, where the input-output voltage slope is 1.





Different logic families have different cutoffs that can be considered for design compatibility. Generally, the voltage levels have decreased over time as transistors have gotten smaller.



CMOS transistors

CMOS transistors function as switches. A gate controls the connection between source and drain by moving charges around in an NPN or PNP doped silicon arrangement. The gate and the substrate are separated by SiO2, or glass, thus Metal Oxide Semiconductor.



They can be either nMOS or pMOS, which switch on or off depending on whether the gate is logic 1 or 0.



nMOS are better for passing 0s, so S should be connected to ground. pMOS are better for passing 1s, so S should be connected to VDD. Thus transistors are typically used in the following pattern, where pMOS networks pull an output up to VDD (logic 1) while nMOS networks pull an output down to GND (logic 0).



Building gates

A NOT gate can be built with transistors like this:



Note the pMOS pull up and nMOS pull down design. When A = 1, P1 is closed and N1 is open, pulling Y down to 0. When A = 0, P1 is closed and N1 is closed, pulling Y up to 1, exactly the behavior of a NOT gate.

A NAND gate can be built with parallel pull-up pMOS gates (A or B = 0 results in output 1) and series pull-down nMOS gates (A and B = 1 => Y = 0).



It's actually easier to build NAND than AND due to the pull-down/pull-up constraint. An AND gate can be made by combining NAND and NOT.



A NOR gate has a similar structure to NAND, but instead of parallel pMOS and series nMOS, we have series pMOS and parallel nMOS.





Power usage

Power usage is made up of dynamic (from charging up capacitance when switching) and static (from current leakage) power.

P = \alpha C V_{DD}^2 f + I_{DD} V_{DD}
P=αCVDD2f+IDDVDDP = \alpha C V_{DD}^2 f + I_{DD} V_{DD}

For the dynamic part of this equation,

C C C
is the capacitance of the gate,
f f f
is the clock speed/frequency and
\alpha α \alpha
is the activity rate, how many times the capacitor is charged per cycle.

For the static part,

I_{DD} IDD I_{DD}
is the leakage current.

Example calculation from the slides:



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E85 Digital Design

HMC class w Prof. Smilkstein and Prof. Shia